IoT Roadshow, Austin – Synopsys: Integrated IoT SoCs start with a variety of IP and the right core

What’s most important in an Internet of Things (IoT) edge processor? Energy efficiency? Integrated wireless? Security? Performance?

What type of sensors inputs, security, and connectivity should be included?

The answer to all of the above is, “It depends what you’re building.”

In the last few years we have seen an increasing trend towards highly integrated, highly customized System-on-Chips (SoCs), as decreasing margins and intense competition have forced chip designers to provide more finely tuned silicon for markets they serve. For example, the sensor subsystem and memory requirements of a wearable device are not the same as for a smart home appliance, while the connectivity options for a smart home appliance are completely separate from those used in a smart city earthquake monitor. In order to realize efficiencies in cost, performance, and power while meeting the requirements of their customers, chipmakers are subsequently turning to semiconductor IP vendors to provide comprehensive yet modular IP solutions for the creation of IoT edge processors.

For instance, Synopsys has identified wireless connectivity, security, sensor processing, and energy efficiency as the four key design requirements of an IoT SoC, and grouped its various offerings by edge device class as shown in Figure 1.

[Figure 1 | Synopsys’ IP portfolio is modular and flexible enough to support a range of System-on-Chip (SoC) designs for Internet of Things (IoT) edge devices. Purple blocks denote Synopsys IP offerings.]

Visible in the figure are all of the decisions that go into the development of IoT SoC based on the requirements of a given end market or application. But the constants in any design are attention to performance and power consumption, with the constant quest for more of one and less of the other. Here, Synopsys promotes its ARC line of 32-bit processors that, according to the company, provide three benefits in the context of SoC design:

  1. A bus-less architecture that is tightly coupled with other IP to reduce on-chip communications latency and shrink overall die size, resulting in less power draw
  2. The ability to configure instructions on the processor to optimize performance
  3. The ability to implement custom instructions for specific applications to optimize performance

On points two and three, the instruction flexibility allows designers to stay with smaller, less powerful cores when looking for an extra performance boost, which is evident in the Intel Quark Microcontroller SE that employs a 32-bit ARC EM DSP core with 192 Kb of Flash that offloads sensor processing functions from the Quark’s x86 core (Figure 2). When placed into a sleep state, the ARC DSP’s ability to perform floating-point division, fractional arithmetic, square root calculations, and trigonometric functions yields a sensor processing subsystem that precludes the need for a larger, more power hungry, more expensive central processing core. This architecture is also present on the Intel Curie platform.

[Figure 2 | The Intel Quark Microcontroller SE includes a 32-bit ARC EM DSP core to offload the main core of tasks such as artifact rejection, data averaging, error correction, filtering, and sensor fusion.]

When the IoT Roadshow visited Austin, TX, I sat down with Ron Lowman, IoT Strategic Marketing Manager for Synopsys to discuss how his company is addressing the move towards integrated SoCs for the IoT, as well as the power, performance, and cost tradeoffs in these architectures. He also sheds some light on continued consolidation in the semiconductor industry. Listen to the interview below.