IoT Roadshow, Silicon Valley – Sonics: Power thrashing, the need for speed, and idle power management
Energy efficiency is almost synonymous with cost these days in the tech industry, particularly with the influx of resource-constrained Internet of Things (IoT) devices operating on battery power (or less). Power consumption for these devices can be the difference between profitable margins and sending technicians into the field to replace a coin cell, or consumers growing tired of charging a product and simply not using it anymore.
However, the power consumption problem is not an easy one. Take, for example, the growing requirement for “always-on” sensing in many IoT systems. Even if the system uses a microcontroller (MCU) based on an extremely energy-efficient core and operates at very low duty cycles, in many cases most or all of the core must be fired up (even if seldomly) to check for changes in its surrounding environment. As discussed in the article “Sub-threshold circuitry: Making Moore’s about power, not performance” elsewhere in this issue, the dynamic energy required to change transistor states from on to off is a huge power suck in standard integrated circuits (ICs), and, likewise, transitioning a CPU from sleep or standby to active mode is power drain on a larger scale.
The logical solution here is to wake up only those portions of the processor essential to verifying an environmental status change (which in the case of our sensor system would be a low-resolution analog IP block), while keeping other parts of the chip powered down. This is known as clock gating, a technique typically implemented through interrupt-driven software that shuts off the clock signal to parts of the processor, shutting off that circuitry. However, a drawback to this approach is power thrashing, an incident that occurs when latency in the software-based interrupt cuts the signal to a domain that actually needs to be powered up, resulting in an on-off-on series of power state transitions that is energy inefficient, to say the least. In fact, the transitions cost more power than if the circuit had just remained on.
Given these limitations, engineers at Sonics, Inc. (), an IP company out of Milpitas, CA, took a different approach. Rather than executing dynamic power management techniques such as clock gating, voltage switching, and voltage scaling in software, Sonics developed a granular hardware subsystem that manages circuit idle time to minimize power consumption. They refer to it as an energy processing unit (EPU).
The energy processing unit
As its name suggest, an EPU is focused on power management, but unlike a CPU that governs active processes, an EPU is concerned with idle states.
As a configurable power management subsystem that affords autonomous control over collections of logic, or grains, EPUs allow system-on-chip (SoC) designers to partition a chip into tens or hundreds of grains, enabling power management over each of them individually. These individual grains can be specified as part of a voltage domain, a power domain, a clock gating domain, or all three simultaneously, but more importantly, the hardware-based granularity permits the individual grains to be managed much more quickly than with traditional software-based methods. According to Sonics engineers, EPUs perform power state transitions orders of magnitude more quickly than operating system (OS) or dedicated MCU software, resulting in a virtuous cycle that requires less energy when transitioning between power states and faster time to completion (Figure 1).
[Figure 1 | EPUs such as Sonics’ ICE-G1 enable faster power state transitions that result in significant energy savings.]
How it works
The architecture of EPUs such as the ICE-G1 calls for a dedicated controller that manages the clock and power control of various domains, which also provides the ability to specify additional power states for precision power management (Figure 2). Going back to our sensor subsystem example, the typical “sleep,” “doze,” and “on” power states can be supplemented with states like “wait detect” and “detect” modes in which the clock frequency and duration of the detection period can be carefully controlled (Figure 3). Not only does this imply that the low-resolution analog IP is active for the smallest amount of time, but the grain controller also ensures only that IP block is active unless further action is required.
[Figure 2 | The ICE-G1 EPU contains only one hardware interface and one software interface so it can monitor all signals generated elsewhere on the chip. Its performance is measured in millions of power states per second (MSPS).]
[Figure 3 | Additional power states can be added for maximized energy efficiency.]
In an IoT that is increasingly about resource conservation, the power saved here is as good as gold.